Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.
1. Fundamental Concepts 2. Scalar Data Types and Operations 3. Sequential Statements 4. Composite Data Types and Operations 5. Basic Modeling Constructs 6. Case Study: A Pipelined Complex Multiplier Accumulator 7. Subprograms 8. Packages and Use Clauses 9. Aliases 10. External Names in Testbenches 11. Properties and Assertion-Based Design 12. Resolved Signals 13. Generics 14. Components and Configurations 15. Generate Statements 16. Access Types and Abstract Data Types 17. Files and Input/Output 18. Case Study: Queuing Networks 19. Attributes and Groups 20. Design for Synthesis 21. Case Study: System Design using the Gumnut Core 22. Miscellaneous Topics
Appendix A. Standard Packages B. Related Standards C. VHDL Syntax D. Differences Among VHDL Versions E. Answers to Exercises