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Interconnect Noise Optimization in Nanometer Technologies
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Gewicht:
412 g
Format:
241x160x15 mm
Beschreibung:
This book provides insight into the use of CAD for layout analysis and optimization of interconnect in high speed, high complexity integrated circuits, which have become the dominating factor in determining system performance in nanometer technologies. The text investigates the effects on system performance and reliability of wire size, spacing, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap, frequency, shields, signal direction and wire width for both the aggressors and the victim wires. The authors present a range of CAD algorithms and techniques for synthesizing and optimizing interconnect.
Introduction.- Noise Analysis and Design in Deep Submicron.- Interconnect Noise Analysis and Optimization Techniques.- Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies.- Minimum Area Shield Insertion for Inductive Noise Reduction.- Spacing Algorithms for Crosstalk Noise Reduction.- Post Layout Interconnect Optimization for Crosscoupling Noise Reduction.- 3D Integration. - EDA Industry Tools: State of the Art.
Presents a range of CAD algorithms and techniques for synthesizing and optimizing interconnect
Provides insight & intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits
Provides insight & intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits