Springer Book Archives

1 Introduction to CMOS.- 1.1 Why Study CMOS?.- 1.2 Basic Concepts.- 1.2.1 Switch Logic.- 1.2.2 Logic Transmission.- 1.2.3 Data storage.- 1.2.4 Dynamic CMOS.- 1.2.5 CMOS System Design.- 1.3 Plan of the Book.- 1.4 References.- 2 MOSFET Characteristics.- 2.1 Threshold Voltage.- 2.1.1 Body-Bias.- 2.2 Current-Voltage Characteristics.- 2.2.1 Square-Law Model.- 2.2.2 Bulk-Charge Model.- 2.3 p-Channel MOSFETs.- 2.4 MOSFET Capacitances.- 2.4.1 MOS-Based Capacitances.- 2.4.2 Depletion Capacitance.- 2.4.3 Channel Capacitances.- 2.4.4 Device Model.- 2.5 Junction Leakage Currents.- 2.6 Parasitic Resistances.- 2.6.1 Drain and Source Resistance.- 2.6.2 Contact Resistance.- 2.7 Non-Rectangular MOSFET Gates.- 2.8 Mobility Variations.- 2.8.1 Velocity-Saturation Effects.- 2.8.2 Gate Voltage Reduction.- 2.9 Subthreshold Current.- 2.10 Temperature Dependence.- 2.11 Scaling Theory.- 2.11.1 Full-Voltage Scaling.- 2.11.2 Constant-Voltage Scaling.- 2.11.3 Second-Order Scaling Effects.- 2.12 Short-Channel Effects.- 2.12.1 Short-Channel Definition.- 2.12.2 Threshold Voltage Reduction.- 2.12.3 Short-Channel MOSFET Model.- 2.13 Narrow-Width Threshold Voltage.- 2.14 Hot Electrons.- 2.15 MOSFET Modelling in SPICE.- 2.15.1 SPICE2 MOSFET Model.- 2.15.2 BSIM.- 2.16 References.- 3 The CMOS Inverter.- 3.1 Circuit Operation.- 3.1.1 DC Inverter Calculations.- 3.1.2 Symmetrical Inverter.- 3.2 Inverter Switching Characteristics.- 3.2.1 Switching Intervals.- 3.3 Output Capacitance.- 3.4 Secondary Parasitic Effects.- 3.4.1 Leakage Currents.- 3.4.2 Parasitic Resistances.- 3.5 Comparison with SPICE.- 3.5.1 Capacitances.- 3.5.2 MOSFET Models.- 3.5.3 Input Waveforms.- 3.6 Inverter Design.- 3.7 The Power-Delay Product.- 3.8 Temperature Dependence.- 3.9 References.- 4 Static Logic Circuits.- 4.1 General Structure.- 4.2 Series-Connected MOSFETs.- 4.2.1 Discharging Through an nMOS Chain.- 4.2.2 Charging Through a pMOS Chain.- 4.2.3 Body-Bias Effects.- 4.3 NAND Gate.- 4.3.1 DC Characteristics.- 4.3.2 Transient Characteristics.- 4.3.3 Design.- 4.3.4 N-Input NAND.- 4.4 NOR Gate.- 4.4.1 DC Characteristics.- 4.4.2 Transient Times.- 4.4.3 Design.- 4.4.4 N-Input NOR.- 4.5 Comparison of NAND and NOR Gates.- 4.6 OR and AND Gates.- 4.7 Combinational Logic.- 4.7.1 Logic Formation.- 4.7.2 Canonical Logic Forms.- 4.7.3 Circuit Design.- 4.8 Exclusive-OR and Equivalence.- 4.9 Structural Variations.- 4.10 Tri-State Output.- 4.11 Pseudo-nMOS/pMOS Logic.- 4.11.1 Pseudo-nMOS.- 4.11.2 Pseudo-pMOS.- 4.12 Flip-Flops.- 4.13 Schmitt Trigger.- 4.14 References.- 5 CMOS Switch Logic.- 5.1 CMOS Transmission Gates.- 5.1.1 nMOS Transmission Properties.- 5.1.2 pMOS Transmission Characteristics.- 5.2 Transmission Gate Model.- 5.2.1 Equivalent Resistance.- 5.2.2 Load Capacitance.- 5.3 Layout Considerations.- 5.4 TG-Based Switch Logic Gates.- 5.4.1 Path Selector.- 5.4.2 OR Gate.- 5.4.3 XOR and Equivalence.- 5.4.4 Adders.- 5.5 Latches and Flip-Flops.- 5.5.1 Basic Latch.- 5.5.2 D Flip-Flop.- 5.5.3 Toggle Flip-Flop.- 5.5.4 JK Flip-Flop.- 5.6 Array Logic.- 5.6.1 Multiplexers/Demultiplexers.- 5.6.2 Split Arrays.- 5.7 Differential CVS Logic.- 5.7.1 Basic Operation.- 5.7.2 Logic Design.- 5.8 Complementary Pass-Transistor Logic.- 5.9 DSL Logic.- 5.10 References.- 6 Chip Design.- 6.1 Isolation.- 6.1.1 LOCOS.- 6.1.2 Trench Isolation.- 6.2 CMOS Process Examples.- 6.2.1 Bulk CMOS.- 6.2.2 Latchup.- 6.2.3 Silicon-On-Insulator (SOI) Techniques.- 6.3 Design Rules.- 6.3.1 Lithography and Fabrication.- 6.3.2 Basic Design Rule Set.- 6.4 Basic Layout.- 6.4.1 General Layout Strategies.- 6.4.2 Equivalent Load Concept.- 6.4.3 Latchup Prevention.- 6.4.4 Static Gate Layout.- 6.4.5 TG-Based Logic.- 6.5 Interconnects.- 6.5.1 Parasitics.- 6.5.2 Interconnect Levels.- 6.6 Data Transmission.- 6.6.1 Basic Model.- 6.6.2 Lumped-Element Analysis.- 6.7 Transmission Line Analysis.- 6.7.1 Wave Properties.- 6.7.2 Basic Properties.- 6.7.3 Capacitive Load.- 6.7.4 Transmission Line Drivers.- 6.7.5 RC Lines.- 6.8 Crosstalk.- 6.8.1 Origin of Crosstalk.- 6.8.2 Interconnect Coupling.- 6.8.3 Circuit Coupling.- 6.9 Gate Arrays in CMOS.- 6.10 References.- 7 Synchronous Logic.- 7.1 Clock Signals.- 7.2 Clock Distribution and Skew.- 7.3 Clocked Static Logic.- 7.3.1 Design Factors.- 7.3.2 Complex Logic Cascades.- 7.4 Charge Storage Nodes.- 7.5 Charge Leakage.- 7.5.1 Constant Current and Capacitance.- 7.5.2 Voltage-Dependent Current.- 7.5.3 Complete Solution.- 7.5.4 Single-Polarity MOSFET Storage Nodes.- 7.6 Charge Sharing.- 7.7 Dynamic Logic.- 7.7.1 Dynamic nMOS Inverter.- 7.7.2 Dynamic pMOS Inverter.- 7.7.3 Complex Logic.- 7.7.4 Dynamic Cascades.- 7.8 Domino Logic.- 7.8.1 Analysis.- 7.8.2 Maximum Clock Frequency.- 7.8.3 Transistor Sizing.- 7.8.4 Charge Leakage and Charge Sharing.- 7.9 Multiple-Output Domino Logic.- 7.9.1 MODL Carry-Look-Ahead Adder.- 7.10 Latched Domino Logic.- 7.11 NORA Logic.- 7.11.1 Signal Races.- 7.11.2 Data Control Using Dynamic Latches.- 7.11.3 Clocked-CMOS Latches.- 7.11.4 NORA Structuring.- 7.11.5 NORA Serial Adder.- 7.11.6 NORA Serial-Parallel Multiplier.- 7.12 Zipper CMOS Logic.- 7.13 References.- 8 Design of Basic Circuits.- 8.1 Chip Floorplan.- 8.2 Input Protection Circuits.- 8.3 Static Gate Sizing.- 8.3.1 Single Inverter Model.- 8.3.2 Inverter Chain Analysis.- 8.3.3 Application of the Results.- 8.4 Off-Chip Driver Circuits.- 8.4.1 Basic Off-Chip Driver Design.- 8.4.2 Tri-State and Bidirectional I/O.- 8.5 Timing and Clock Distribution.- 8.5.1 Clocks and Timing Circles.- 8.5.2 Clock Generation Circuits.- 8.5.3 Clock Drivers and Distribution Techniques.- 8.6 Memory Circuits.- 8.6.1 Static RAM Cell.- 8.6.2 Dynamic RAM Cell.- 8.6.3 Architecture.- 8.6.4 Address Decoders.- 8.6.5 Column Selector and Sense Amplifiers.- 8.6.6 Summary.- 8.7 References.- 9 Analog CMOS Circuits.- 9.1 MOSFET Equations.- 9.2 Small-Signal MOSFET Model.- 9.3 Basic Amplifier.- 9.3.1 Small-Signal Gain.- 9.3.2 Frequency Response.- 9.4 Voltage References.- 9.5 Current Sources.- 9.6 Differential Amplifier.- 9.7 A CMOS Operational Amplifier.- 9.8 Summary.- 9.9 References.- 10 BiCMOS Circuits.- 10.1 Bipolar Junction Transistors.- 10.1.1 Structure and Operation.- 10.1.2 Bipolar Transistor Capacitances.- 10.2 BiCMOS Technology.- 10.3 BiCMOS Inverter.- 10.3.1 DC Characteristics.- 10.3.2 Transient Switching Characteristics.- 10.4 Comparison of CMOS and BiCMOS Performance.- 10.5 Circuit Variations.- 10.5.1 Pull-Down MOSFETs.- 10.5.2 Logic Swing.- 10.6 Logic Formation.- 10.6.1 NAND Gate.- 10.6.2 NOR Gate.- 10.6.3 AOI and OAI Logic.- 10.6.4 Pseudo-nMOS Input Circuits.- 10.7 Tri-state Output.- 10.8 Level Conversion.- 10.9 Summary.- 10.10 References.

During the last decade, CMOS has become increasingly attractive as a basic integrated circuit technology due to its low power (at moderate frequencies), good scalability, and rail-to-rail operation. There are now a variety of CMOS circuit styles, some based on static complementary con ductance properties, but others borrowing from earlier NMOS techniques and the advantages of using clocking disciplines for precharge-evaluate se quencing. In this comprehensive book, the reader is led systematically through the entire range of CMOS circuit design. Starting with the in dividual MOSFET, basic circuit building blocks are described, leading to a broad view of both combinatorial and sequential circuits. Once these circuits are considered in the light of CMOS process technologies, impor tant topics in circuit performance are considered, including characteristics of interconnect, gate delay, device sizing, and I/O buffering. Basic circuits are then composed to form macro elements such as multipliers, where the reader acquires a unified view of architectural performance through par allelism, and circuit performance through careful attention to circuit-level and layout design optimization. Topics in analog circuit design reflect the growing tendency for both analog and digital circuit forms to be combined on the same chip, and a careful treatment of BiCMOS forms introduces the reader to the combination of both FET and bipolar technologies on the same chip to provide improved performance.