1 Introduction.- 1.1 Problems of Interest.- 1.2 Organization.- I Equivalence Checking.- 2 Symbolic Verification.- 3 Incremental Verification for Combinational Circuits.- 4 Incremental Verification for Sequential Circuits.- 5 AQUILA: A Local BDD-based Equivalence Verifier.- 6 Algorithm for Verifying Retimed Circuits.- 7 RTL-to-Gate Verification 123.- II Logic Debugging.- 8 Introduction to Logic Debugging.- 9 ErrorTracer: Error Diagnosis by Fault Simulation.- 10 Extension to Sequential Error Diagnosis.- 11 Incremental Logic Rectification.

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley