che-chandler.de
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Paperback
Print on Demand | Lieferzeit: Print on Demand - Lieferbar innerhalb von 3-5 Werktagen I
Alle Preise inkl. MwSt. | Versandkostenfrei
Nicht verfügbar
Zum Merkzettel
Gewicht:
300 g
Format:
235x155x11 mm
Beschreibung:
This book presents fresh research techniques, algorithms, methodologies and experimental results for high-level power estimation and power-aware high-level synthesis. The book will help get products to market quicker and facilitate low-power ASIC/FPGA design.
Integrates power estimation and reduction for high level synthesis, with low-power, high-level design
Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.
This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.