Edited by key figures in 3D integration and written by top authors from high-tech companies and renowned research institutions, this book covers the intricate details of 3D process technology. As such, the main focus is on silicon via formation, bonding and debonding, thinning, via reveal and backside processing, both from a technological and a materials science perspective. The last part of the book is concerned with assessing and enhancing the reliability of the 3D integrated devices, which is a prerequisite for the large-scale implementation of this emerging technology. Invaluable reading for materials scientists, semiconductor physicists, and those working in the semiconductor industry, as well as IT and electrical engineers.

Edited by key figures in 3D integration and written by top authors from high-tech companies and renowned research institutions, this book covers the intricate details of 3D process technology.As such, the main focus is on silicon via formation, bonding and debonding, thinning, via reveal and backside processing, both from a technological and a materials science perspective. The last part of the book is concerned with assessing and enhancing the reliability of the 3D integrated devices, which is a prerequisite for the large-scale implementation of this emerging technology.Invaluable reading for materials scientists, semiconductor physicists, and those working in the semiconductor industry, as well as IT and electrical engineers.

3D IC INTEGRATION SINCE 20083D IC NomenclatureProcess StandardizationThe Introduction of Interposers (2.5D)The FoundriesMemoryThe Assembly and Test Houses3D IC Application RoadmapsKEY APPLICATIONS AND MARKED TRENDS FOR 3D INTEGRATION AND INTERPOSER TECHNOLOGIESIntroductionAdvanced Packaging Importance in the Semiconductor Industry is Growing3D Integration-Focused Activities - The Global IP LandscapeApplications, Technology, and Market TrendsECONOMIC DRIVERS AND IMPEDIMENTS FOR 2.5D/3D INTEGRATION3D Performance AdvantagesThe Economics of ScalingThe Cost of Future ScalingCost Remains the Impediment to 2.5D and 3D Product IntroductionINTERPOSER TECHNOLOGYDefinition of 2.5D InterposersInterposer Drivers and NeedComparison of Interposer MaterialsSilicon Interposers with TSVLower Cost InterposersInterposer Technical and Manufacturing ChallengesInterposer Application ExamplesConclusionsTSV FORMATION OVERVIEWIntroductionTSV Process ApproachesTSV Fabrication StepsYield and ReliabilityTSV UNIT PROCESSES AND INTEGRATIONIntroductionTSV Process OverviewTSV Unit ProcessesIntegration and Co-Optimization of Unit Processes in Via Formation SequenceCo-Optimization of Unit Processes in Backside Processing and Via-Reveal FlowIntegration and Co-Optimization of Unit Processes in Via-Last FlowIntegration with PackagingElectrical Characterization of TSVsConclusionsTSV FORMATION AT ASETIntroductionVia-Last TSV for Both D2D and W2W Processes in ASETTSV Process for D2DTSV Process for W2WConclusionsLASER-ASSISTED WAFER PROCESSING: NEW PERSPECTIVES IN THROUGH-SUBSTRATE VIA DRILLING AND REDISTRIBUTION LAYER DEPOSITIONIntroductionLaser Drilling of TSVsDirect-Write Deposition of Redistribution LayersConclusions and OutlookTEMPORARY BONDING MATERIAL REQUIREMENTSIntroductionTechnology OptionsRequirements of a Temporary Bonding MaterialConsiderations for Successful ProcessingSurviving the Backside ProcessDebondingTEMPORARY BONDING AND DEBONDING - AN UPDATE ON MATERIALS AND METHODSIntroductionCarrier Selection for Temporary BondingSelection of Temporary Bonding AdhesivesBonding and Debonding ProcessesEquipment and Process IntegrationZONEBOND®: RECENT DEVELOPMENTS IN TEMPORARY BONDING AND ROOM-TEMPERATURE DEBONDINGIntroductionThin Wafer ProcessingZoneBOND Room-Temperature DebondingConclusionsTEMPORARY BONDING AND DEBONDING AT TOKIntroductionZero Newton TechnologyConclusionsTHE 3M (TM) WAFER SUPPORT SYSTEM (WSS)IntroductionSystem DescriptionGeneral AdvantagesHigh-Temperature Material SolutionsProcess ConsiderationsFuture DirectionsSummaryCOMPARISON OF TEMPORARY BONDING AND DEBONDING PROCESS FLOWSIntroductionStudies of Wafer Bonding and ThinningBackside ProcessingDebonding and CleaningTHINNING, VIA REVEAL, AND BACKSIDE PROCESSING - OVERVIEWIntroductionWafer Edge TrimmingThin Wafer Support SystemsWafer ThinningThin Wafer Backside ProcessingBACKSIDE THINNING AND STRESS-RELIEF TECHNIQUES FOR THIN SILICON WAFERSIntroductionThin Semiconductor DevicesWafer Thinning TechniquesFracture Tests for Thin Silicon WafersComparison of Stress-Relief Techniques for Wafer Backside ThinningProcess Flow for Wafer Thinning and DicingSummary and Outlook on 3D IntegrationVIA REVEAL AND BACKSIDE PROCESSINGIntroductionVia Reveal and Backside Processing in Via-Middle ProcessBackside Processing in Back-Via ProcessBackside Processing and Impurity GetteringBackside Processing for RDL FormationDICING, GRINDING, AND POLISHING (KIRU KEZURU AND MIGAKU)IntroductionGrinding and PolishingDicingSummaryOVERVIEW OF BONDING AND ASSEMBLY FOR 3D INTEGRATIONIntroductionDirect, Indirect, and Hybrid BondingRequirements for Bonding Process and MaterialsBonding Quality CharacterizationDiscussion of Specific Bonding and Assembly TechnologiesSummary and ConclusionsBONDING AND ASSEMBLY AT TSMCIntroductionProcess FlowChip-on-Wafer StackingCoW-on-Substrate (CoWoS) StackingCo