This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration.

This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective.Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration.

PART I: Design# 01 3D Design Styles# 02 Ultra-Fine Pitch 3D-Stacked Integrated Circuits: Technology, Design Enablement and Application# 03 Power Delivery Network and Integrity in 3D IC Chips# 04 Multiphysics Challenges and Solutions for Design of Heterogeneous 3D-Integrated Systems# 05 Physical Design Flow for 3D/CoWoS¿ Stacked ICs# 06 Design and CAD Solutions for Cooling and Power Delivery for Monolithic 3D Ics# 07 Electronic Design Automation for 3D# 08 3D Stacked DRAM MemoriesPART II: Test# 09 Cost Modelling for 2.5D and 3D Stacked ICs# 10 Interconnect Testing for 2.5D- and 3D-SICs# 11 Pre-Bond Testing Through Direct Probing of Large-Array Fine-Pitch Micro-Bumps# 12 3D Design-for-Test Architecture# 13 Optimization of Test-Access Architectures and Test Scheduling for 3D ICs# 14 IEEE P1838 3D Test Access Standard-in-Development# 15 Test and Debug Strategy for TSMC CoWoS¿ Stacking Process Based Heterogeneous 3D IC: A Silicon StudyPART III: Thermal Management# 16 Thermal isolation and cooling technologies for heterogeneous 3-D and 2.5-D ICs# 17 Passive and Active Thermal Technologies: Modeling and Evaluation# 18 Thermal Modeling and Experimental Model Validation for 3D Stacked ICs# 19 On the Thermal Management of 3D ICs: from back-side, to volumetric heat removal