Entropy Coders of the H.264/AVC Standard
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Entropy Coders of the H.264/AVC Standard

Algorithms and VLSI Architectures
 eBook
Sofort lieferbar | Lieferzeit: Sofort lieferbar I
ISBN-13:
9783642147036
Veröffentl:
2010
Einband:
eBook
Seiten:
180
Autor:
Xiaohua Tian
Serie:
Signals and Communication Technology
eBook Typ:
PDF
eBook Format:
Reflowable eBook
Kopierschutz:
Digital Watermark [Social-DRM]
Sprache:
Englisch
Beschreibung:

This book presents an Entropy Encoder for the H.264 or MPEG-4 standard, starting with the fundamentals and a review on existing code design. It opens a way to impressive compression performance and new multimedia applications.

This book presents a collection of algorithms and VLSI architectures of entropy (or statistical) codecs of recent video compression standards, with focus on the H.264/AVC standard. For any visual data compression scheme, there exists a combination of two, or all of the following three stages: spatial, temporal, and statistical compression. General readers are first introduced with the various algorithms of the statistical coders. The VLSI implementations are also reviewed and discussed. Readers with limited hardware design background are also introduced with a design methodology starting from performance-complexity analyses to software/hardware co-simulation. A typical design of the Contextbased Adaptive Binary Arithmetic Coding (CABAC) encoder is also presented in details. To support System-on-Chip design environment, the CABAC design is wrapped with a SoC-based Wishbone system bus interface.

Introduction to Video Compression.- Review of Arithmetic Coding and CABAC.- Review of Existing Statistical Codec Designs.- Design of a CABAC Encoder.- Efficient Architecture of Context Modeling of CABAC Encoder.- Design of System Bus Interface & Inter-connection of SoCbased CABAC Encoder.

This book presents a collection of algorithms and VLSI architectures of entropy (or statistical) codecs of recent video compression standards, with focus on the H.264/AVC standard. For any visual data compression scheme, there exists a combination of two, or all of the following three stages: spatial, temporal, and statistical compression. General readers are first introduced with the various algorithms of the statistical coders. The VLSI implementations are also reviewed and discussed. Readers with limited hardware design background are also introduced with a design methodology starting from performance-complexity analyses to software/hardware co-simulation. A typical design of the Contextbased Adaptive Binary Arithmetic Coding (CABAC) encoder is also presented in details. To support System-on-Chip design environment, the CABAC design is wrapped with a SoC-based Wishbone system bus interface.

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